The present subject matter relates to semiconductor design technology; and, particularly, to a detection circuit for detecting a threshold voltage of a semiconductor device and an internal voltage generating circuit using the same, and more particularly, to a circuit for generating a boosted voltage by changing a target level depending on the level of a threshold voltage of the semiconductor device.
Generally, a dynamic RAM (hereinafter, referred to as “DRAM”) uses one capacitor and one MOS transistor as a unit storage device for recording data, which is called a cell.
When data of ‘1’ or logic ‘high level’ is stored in the cell, a high potential, generally, a core voltage VCORE is applied to the capacitor, and when a data of ‘0’ or logic ‘low level is stored in the cell, a low potential, generally, a ground voltage VSS is applied to the capacitor.
At this time, a MOS transistor included in each cell operates as a switch. When a voltage higher than a predetermined level is applied to a word line, the MOS transistor is turned on to connect the capacitor and a bit line. In other words, charge is shared between the capacitor and the bit line so that the electric potential applied to the capacitor is renewed.
Likewise, when a voltage lower than a predetermined level is applied to the word line, the MOS transistor is turned off not to connect the capacitor and the bit line. In other words, charge is not shared between the capacitor and the bit line, so that the capacitor maintains the electric potential renewed upon charge sharing.
FIG. 1 is a detailed circuit diagram showing a cell configuration of a conventional semiconductor device.
Referring to FIG. 1, a cell of the general semiconductor device includes an NMOS transistor TCN and a capacitor CS.
Concretely, in the NMOS transistor TCN, a gate and a word line are connected, a drain and the capacitor CS are connected, and a source and a bit line are connected. In its operation, when the word line connected to the gate is activated and a boosted voltage VPP is applied to the word line, the NMOS transistor TCN controls the connection of the bit line and the capacitor CS, which are connected to the drain and source, respectively, in response to the boosted voltage VPP.
As described above, a high potential, generally, a core voltage VCORE, and a low potential, generally, a ground voltage VSS, are charged in the capacitor CS, and a bit line precharge voltage VBLP is applied to the bit line. Further, the level of the bit line precharge voltage VBLP is generally equal to a half the level of the core voltage VCORE.
Therefore, when the bit line and the capacitor CS are connected by the NMOS transistor TCN, if the voltage charged in the capacitor CS is the core voltage VCORE, charge is transferred from the capacitor CS to the bit line and if the voltage charged in the capacitor CS is the ground voltage VSS, charge is transferred from the bit line to the capacitor CS.
In this way, the NMOS transistor TCN operates as a switch between the bit line and the capacitor CS, controls such that charge flows between the bit line and the capacitor CS when a boosted voltage VPP is applied to the word line connected to the gate, and controls such that no charge flows between the bit line and the capacitor CS when no boosted voltage VPP is applied to the word line.
By the way, in order that the NMOS transistor TCN operates as a switch to transfer charge between the bit line and the capacitor CS without any loss, a predetermined level of the boosted voltage VPP to be applied to the word line should satisfy the following condition.
That is, a predetermined level of the boosted voltage VPP must be a value obtained by adding a level of a threshold voltage VTH which is a minimum voltage required to control such that charge flows between the drain and source of the NMOS transistor TCN, a level of a core voltage VCORE, which is a maximum voltage that can be transferred between the bit line and the capacitor CS, and a given voltage a, which is a voltage that is added in order to transfer charge between the bit line and the capacitor CS without any loss even when a level of the boosted voltage VPP sharply drops by the operation of the semiconductor device.
This can be expressed as:VPP=VCORE+VTH+a   Eq. (1)
Meanwhile, most semiconductor devices including the aforementioned DRAM use a method of supplying by itself voltages required for the operation of in-chip circuits by being provided with, in a chip, an internal voltage generating circuit for generating an internal voltage of various electric potentials using a power supply voltage VDD supplied from the outside and a ground voltage VSS.
In other words, the aforementioned boosted voltage VPP is also generated through a boosted voltage generating circuit within a semiconductor device.
FIG. 2 is a block diagram showing a conventional boosted voltage generating circuit for a semiconductor device.
Referring to FIG. 2, the conventional boosted voltage generating circuit 10 for a semiconductor device includes a boosted voltage detector 100 for detecting a level of a boosted voltage VPP and a boosted voltage output unit 120 for outputting a boosted voltage VPP by controlling the execution of a charge pumping operation in response to an output signal DET_VPP of the boosted voltage detector 100.
The boosted voltage output unit 120 is provided with an oscillator 122 for outputting an oscillation signal OSC toggling in a predetermined cycle in response to the output signal DET_VPP of the boosted voltage detector 100 and a pumping unit 124 for rising a level of the boosted voltage VPP by performing a charge pumping operation in response to the oscillation signal OSC.
Based on the above-described construction, the operation of the conventional boosted voltage VPP generating circuit 10 for a semiconductor device will be described below in detail.
First, the boosted voltage detector 100 compares a level of the boosted voltage VPP with a target reference voltage VREFP to determine a level of the output signal DET_VPP depending on the comparison result.
For instance, when a level of the boosted voltage VPP feedbacked from the boosted voltage output unit 120 is higher than a level of the target reference voltage VREFP, a level of the output signal DET_VPP is transited to logic high and outputted.
Similarly, when a level of the boosted voltage VPP feedbacked from the boosted voltage output unit 120 is lower than a level of the target reference voltage VREFP, a level of the output signal DET_VPP is shifted to logic low and outputted.
Here, the reference voltage VREFP is generally a voltage which is generated from a band gap circuit of a semiconductor device, and always maintains a stable voltage level regardless of PVT (process, voltage, and temperature) variations of the semiconductor device.
Among the components of the boosted voltage output unit 120, the oscillator 122 outputs the oscillation signal OSC toggling in a predetermined cycle in response to the level of the output signal DET_VPP of the boosted voltage detector 100.
Further, among the components of the boosted voltage output unit 120, the pumping unit 124 generates the boosted voltage VPP by performing a charge pumping operation in response to the toggling of the oscillation signal OSC.
For example, if the level of the output signal DET_VPP of the boosted voltage detector 100 is logic ‘low’, the oscillation signal OSC outputted from the oscillator 122 among the components of the boosted voltage output unit 120 does not oscillate in a predetermined cycle but fixed to logic ‘low’ or logic ‘high’.
Therefore, the pumping unit 124 among the components of the boosted voltage output unit 120 does not perform the charge pumping operation, and thus, the level of the boosted voltage VPP drops due to natural discharge or use in the semiconductor device.
Likewise, if the level of the output signal DET_VPP of the boosted voltage detector 100 is logic ‘high’, the oscillation signal OSC outputted from the oscillator 122 among the components of the boosted voltage output unit 120 oscillates in a predetermined cycle.
Thus, the pumping unit 124 among the components of the boosted voltage output unit 120 performs the charge pumping operation, and accordingly, the level of the boosted voltage VPP rises.
FIG. 3 is a detailed circuit diagram showing the boosted voltage detector among the components of the conventional boosted voltage generating circuit for a semiconductor device shown in FIG. 2.
Referring to FIG. 3, among the components of the conventional boosted voltage generating circuit 10 for a semiconductor device, the boosted voltage detector 100 includes a voltage divider 102 for dividing a boosted voltage VPP at a predetermined ratio to generate a divided voltage DIV_VPP and a voltage comparator 104 for comparing levels of a reference voltage VREFP corresponding to a target level of the boosted voltage VPP and the divided voltage DIV_VPP to output a boosted voltage detection signal DET_VPP, the level of which is determined based on the comparison result.
More specifically, the voltage divider 102 is provided with first and second fixed resistors R1 and R2 connected in series between a boosted voltage VPP end and a ground voltage VSS end and having a predetermined resistance, and outputs the divided voltage DIV_VPP at a connection node of the first fixed resistor R1 and the second fixed resistor R2.
Further, the voltage comparator 104 is provided with a unit amplifier 1042 for changing the level of a voltage applied to an output node OUTN corresponding to a level difference between the divided voltage DIV_VPP and the reference voltage VREFP corresponding to the target level of the boosted voltage VPP and a driver 1044 for driving the boosted voltage detection signal DET_VPP in response to the level of the voltage applied to the output node OUTN.
The unit amplifier 1042 is a current mirror type unit amplifier, and is composed of a first NMOS transistor N1 whose gate receives the divided voltage DIV_VPP, a second NMOS transistor N2 whose gate receives the reference voltage VREFP corresponding to the target level of the boosted voltage VPP, a third NMOS transistor N3 whose gate takes a bias voltage Vbias and for controlling the connection of a common node COMM of the drain and source and the ground voltage VSS end in response to the bias voltage Vbias, a first PMOS transistor P1 operating as a diode as the gate and the drain are connected between the power supply voltage VDD end and an intermediate node ZN connected to the drain of the first NMOS transistor N1, and a second PMOS transistor P2 whose gate takes the voltage applied to the intermediate node ZN and for controlling the level of a voltage to be applied to the output node OUTN by controlling the connection of the power supply voltage VDD end and the output node OUTN in response to the voltage applied to the gate.
The driver 1044 is provided with an inverter INV for driving the boosted voltage detection signal DET_VPP in response to the level of the voltage applied to the output node OUTN.
On the basis of the above-described configuration, the operation of the boosted voltage detector 100 among the components of the conventional boosted voltage VPP generating circuit 10 for the semiconductor device will be described below in detail.
For reference, the voltage divider 102 divides the boosted voltage VPP at a predetermined ratio through the first and second fixed resistors R1 and R2. Generally, the first and second fixed resistors R1 and R2 control the level of the divided voltage DIV_VPP to be equal to a half the level of the boosted voltage VPP by having the same resistance.
However, the first and second fixed resistors R1 and R2 do not need to have the same resistance, but may have different resistances. That is, it is possible to change their resistances upon design thereof.
Moreover, it is also possible to divide the boosted voltage VPP by adjusting the predetermined ratio thereof by using more resistors than the first and second fixed resistors R1 and R2, for example, three or four resistors.
First, when the level of the boosted voltage VPP is sufficiently higher than a predetermined level, i.e., the level of the divided voltage DIV_VPP is higher than the level of the reference voltage VREFP corresponding to a target level of the boosted voltage VPP, if the semiconductor device enables a word line by using the boosted voltage VPP, the level of the boosted voltage VPP starts to drop. In other words, the level of the divided voltage DIV_VPP starts to drop.
As the level of the divided voltage DIV_VPP drops like this, it becomes lower than the level of the reference voltage VREFP corresponding to the target level of the boosted voltage VPP at a certain instant.
Thus, the amount of current flowing in the output node OUTN and the common node COMM that are connected to the drain and source of the second NMOS transistor N2 receiving the reference voltage VREFP via the gate is greater than the amount of current flowing in the intermediate node ZN and the common node COMM connected to the drain and source of the first NMOS transistor N1 taking the divided voltage DIV_VPP via the gate.
Due to this, the level of a voltage applied to the output node OUTN drops more than the level of a voltage applied to the intermediate node ZN does. The voltage applied to the intermediate node ZN that drops less as above is inputted to the gate of the second PMOS transistor P2 to decrease the amount of current flowing between the power supply voltage VDD end and the output node OUTN that are connected to the source and drain, thereby much further decreasing the level of the voltage applied to the output node OUTN.
Like this, if the level of the voltage applied to the output node OUTN decreases and thus drops lower than the threshold voltage level of the inverter INV provided in the driver 1044, the boosted voltage detection signal DET_VPP driven by the inverter INV provided in the driver 1044 becomes logic ‘high’, wherein the threshold voltage level is a level at which the inverter INV is able to distinguish logic ‘high’ and logic ‘low’ of the inverter INV provided at the driver 1044, for example, a signal inputted at 0.5 V or less is recognized as logic ‘low’ to make an output signal fall to logic ‘high’, while a signal inputted at 1.2 V or more is recognized as logic ‘high’ to make an output signal fall to logic ‘low’.
Next, when the level of the boosted voltage VPP is sufficiently lower than a predetermined level, i.e., the level of the divided voltage DIV_VPP is lower than the level of the reference voltage VREFP corresponding to a target level of the boosted voltage VPP, if the pumping unit 124 among the components of the boosted voltage output unit 120 performs a charge pumping operation, the level of the boosted voltage VPP starts to rise. In other words, the level of the divided voltage DIV_VPP starts to rise.
As the level of the divided voltage DIV_VPP rises, it becomes higher than the level of the reference voltage VREFP corresponding to the target level of the boosted voltage VPP at a certain instant.
Accordingly, the amount of current flowing in the output node OUTN and the common node COMM that are connected to the drain and source of the second NMOS transistor N2 receiving the reference voltage VREFP via the gate is smaller than the amount of current flowing in the intermediate node ZN and the common node COMM that are connected to the drain and source of the first NMOS transistor N1 receiving the divided voltage DIV_VPP via the gate.
Due to this, the level of the voltage applied to the intermediate node ZN drops more than the level of a voltage applied to the output node OUTN does. The voltage applied to the intermediate node ZN that drops more as above is inputted to the gate of the second PMOS transistor P2 to increase the amount of current flowing between the power supply voltage VDD end and the output node OUTN that are connected to the source and drain, thereby allowing a larger amount of current than the amount of current flowing from the output node OUTN to the common node COMM to flow from the power supply voltage VDD end to the output node OUTN by the second NMOS transistor N2.
Like this, if the level of the voltage applied to the output node OUTN increases and thus rises higher than the threshold voltage level of the inverter INV provided in the driver 1044, the boosted voltage detection signal DET_VPP driven by the inverter INV provided in the driver 1044 becomes logic ‘low’.
As described above, the boosted voltage detector 100 performs the operation of varying the logic level of the output signal DET_VPP so that the boosted voltage VPP can always maintain a predetermined level on the basis of the level of the reference voltage VREFP generated by a band gap circuit corresponding to a target level of the boosted voltage VPP.
At this time, the predetermined level of the boosted voltage VPP is determined by a predetermined level of the core voltage VCORE, a threshold voltage VTH of the NMOS transistor TCN used in a cell array, and the given voltage a, as seen in FIG. 3 and Eq. (1).
For instance, if the predetermined level of the core voltage VCORE is 1.8 V, the threshold voltage of the NMOS transistor TCN is 0.7 V and the given voltage a is 0.9 V, the predetermined level of the boosted voltage VPP becomes 3.4 V, which is obtained by adding all the values.
Further, once the predetermined level of the boosted voltage VPP is determined, a predetermined level of the divided voltage DIV_VPP generated by dividing the boosted voltage VPP at a predetermined ratio is determined as well. If the predetermined ratio is 1/2, the predetermined level of the divided voltage DIV_VPP is 1.7 V, and if it is 1/3, the predetermined level thereof is 1.13 V.
Since the predetermined ratio for generating the divided voltage DIV_VPP is determined by using a fixed resistor having a predetermined resistance, the fixed resistor has to be replaced by redesigning in order to vary the predetermined ratio. That is, it is difficult to vary the predetermined ratio.
Further, the level of the reference voltage VREFP used for comparison of the divided voltage DIV_VPP in the boosted voltage detector 100 is equal to a predetermined level of the divided voltage DIV_VPP. It is apparent that while the level of the divided voltage DIV_VPP varies according to variations of the level of the boosted voltage VPP, the level of the reference voltage VREFP is always constant regardless of level variations of the boosted voltage VPP and PVT variations.
Thus, in order to vary the level of the reference voltage VREFP that is determined once, it is necessary to adjust the size of various devices, such as MOS transistors, resistors, capacitors, etc., in the band gap circuit by redesigning. That is, it is difficult to vary the level of the reference voltage VREFP.
By the way, when producing a cell array of a semiconductor device through an actual process, it is possible to vary the threshold voltage VTH of the NMOS transistor TCN used in the cell array for each wafer.
For example, although a predicted threshold voltage is designed to be 0.7 V, the threshold voltage VTH may vary between 0.5 V and 0.9 V in products produced by an actual process.
However, at the time of design, the level of the threshold voltage VTH is designed to be constantly fixed, and thus, variations of the level of the threshold voltage VTH by a process cannot be reflected in design.
For example, the boosted voltage generating circuit 10 is unable to recognize a variation of the level of the threshold voltage VTH between 0.5 V and 0.9 V, and operates such that a predetermined level of the boosted voltage VPP is always 3.4 V.
When a predetermined level of the boosted voltage VPP is fixed regardless of the variation of the level of the threshold voltage VTH used in a cell array, if the level of the threshold voltage VTH is lower than a predetermined level, a boosted voltage VPP that is too higher than a required level is supplied to the cell array, so that unnecessary current is consumed.
Further, if the level of the threshold voltage VTH is higher than a predetermined level, a boosted voltage VPP that is too lower than a required level is supplied to the cell array, so that the operation of the semiconductor device becomes unstable.
Moreover, in the prior art, in order to vary the levels of the boosted voltage VPP, the divided voltage DIV_VPP and the reference voltage VREFP corresponding to variations of the threshold voltage VTH, redesigning has to be made as described above. Thus, it is impossible to apply variations of the level of the threshold voltage VTH to design.